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MOTOROLA M68040 USER’S MANUAL 7- 15
A31–A4
BCLK
SIZ1, SIZ0
TT1, TT0
TM2–TM0
D31–D0
UPA1, UPA0
CIOUT
TS
TIP
TA
R/W
A3
A2–A0
NOTE: The selected device increments the value of A3 and A2.
10 11 0001
C1 C2 C3 C4 C5
TCI
A3, A2 =
Figure 7-11. Line Read Transfer Timing
Clock 1 (C1)
The line read cycle starts in C1. During the first half of C1, the processor places valid
values on the address bus and transfer attributes. For user and supervisor mode
accesses that are translated by the corresponding memory unit, the UPAx signals are
driven with the values from the matching U1 and U0 bits. The TTx and TMx signals
identify the specific access type. The R/W signal is driven high for a read cycle, and the
size signals (SIZx) indicate line size. CIOUT is asserted for a MOVE16 operand read if
the access is identified as noncachable. Refer to Section 3 Memory Management Unit
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