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7- 10 M68040 USER’S MANUAL MOTOROLA
7.4.1 Byte, Word, and Long-Word Read Transfers
During a read transfer, the processor receives data from a memory or peripheral device.
Since the data read for a byte, word, or long-word access is not placed in either of the
internal caches by definition, the processor ignores the level on the transfer cache inhibit
(TCI) signal when latching the data. The bus controller performs byte, word, and long-word
read transfers for the following cases:
Accesses to a disabled cache.
Accesses to a memory page that is specified noncachable.
Accesses that are implicitly noncachable (read-modify-write accesses and accesses
to an alternate logical address space via the MOVES instruction).
Accesses that do not allocate in the data cache on a read miss (table searches,
exception vector fetches, and exception stack deallocation for an RTE instruction).
The first transfer of a line read is terminated with transfer burst inhibit (TBI), forcing
completion of the line access using three additional long-word read transfers.
Figure 7-8 is a flowchart for byte, word, and long-word read transfers. Bus operations are
similar for each case and vary only with the size indicated and the portion of the data bus
used for the transfer. Figure 7-9 is a functional timing diagram for byte, word, and long-
word read transfers.
ADDRESS DEVICE
1) LATCH DATA
ACQUIRE DATA
START NEXT CYCLE
PROCESSOR EXTERNAL DEVICE
PRESENT DATA
TERMINATE CYCLE
1) DECODE ADDRESS
2) PLACE DATA ON APPROPRIATE BYTES OF 
D31–D0 BASED ON SIZEx, A0, AND A1
3) ASSERT TA
1) REMOVE DATA FROM D31–D0
2) NEGATE TA
1) SET R/W TO READ
2) DRIVE ADDRESS ON A31–A0
3) DRIVE USER PAGE ATTRIBUTES ON UPA1, UPA0
4) DRIVE SIZE ON SIZ1, SIZ0 (BYTE, WORD, 
OR LONG WORD)
5) DRIVE TRANSFER TYPE ON TT1, TT0
6) DRIVE TRANSFER MODIFIER ON TM2–TM0
7) CIOUT BECOMES VALID
8) ASSERT TS FOR ONE CLOCK
9) ASSERT TIP
Figure 7-8. Byte, Word, and Long-Word Read Transfer Flowchart
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