The combination of operand size and alignment determines the number of bus cycles
required to perform a particular memory access. Table 7-3 lists the number of bus cycles
required for different operand sizes with all possible alignment conditions for read and
write cycles. The table confirms that alignment significantly affects bus cycle throughput
for noncachable accesses. For example, in Figure 7-5 the misaligned long-word operand
took three bus cycles because the byte offset = $1. If the byte offset = $0, then it would
have taken one bus cycle. The M68040 system designer and programmer should account
for these effects, particularly in time-critical applications.
Table 7-3. Memory Alignment Influence on
Noncachable and Write-Through Bus Cycles
Number of Bus Cycles
Transfer Size $0*$1*$2*$3*
Instruction 1 N/A N/A N/A
Byte Operand 1 1 1 1
Word Operand 1 2 1 2
Long-Word Operand 1 3 2 3
*Where the byte offset (A1 and A0) equals this encoding.
The processor always prefetches instructions by reading a long word from a half-line
address (A2–A0 = $0), regardless of alignment. When the required instruction begins at
the second long word, the processor attempts to fetch the entire half-line (two long words)
although the second long word contains the required instruction.
The transfer of data between the processor and other devices involves the address bus,
data bus, and control signals. The address and data buses are normally parallel,
nonmultiplexed buses, supporting byte, word, long-word, and line (16-byte) bus cycles.
Line transfers are normally performed using an efficient burst transfer, which provides an
initial address and time-multiplexes the data bus to transfer four long words of information
to or from the slave device. Slave devices that do not support bursting can burst-inhibit the
first long word of a line transfer, forcing the bus master to complete the access using three
additional long-word bus cycles. All bus input and output signals are synchronous to the
rising edge of the BCLK signal. The M68040 moves data on the bus by issuing control
signals and using a handshake protocol to ensure correct data movement. The following
paragraphs describe the bus cycles for byte, word, long-word, and line read, write, and
read-modify-write transfers.
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