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MOTOROLA M68040 USER’S MANUAL 7- 7
Figure 7-5 illustrates the transfer of a long-word operand from an odd address requiring
more than one bus cycle. For the first transfer or bus cycle, the SIZx signals specify a byte
transfer, and the byte offset is $1. The slave device supplies the byte and acknowledges
the data transfer. When the processor starts the second cycle, the SIZx signals specify a
word transfer with a byte offset of $2. The next two bytes are transferred during this cycle.
The processor then initiates the third cycle, with the SIZEx signals indicating a byte
transfer. The byte offset is now $0; the port supplies the final byte and the operation is
complete. This example is similar to the one illustrated in Figure 7-6 except that the
operand is word sized and the transfer requires only two bus cycles. Figure 7-7 illustrates
a functional timing diagram for a misaligned long-word read transfer.
DATA BUS
31 0
BYTE 3
BYTE 2 BYTE 1
BYTE 0 —— X
MEMORY
31 0
XXX BYTE 3 BYTE 2 BYTE 1
BYTE 0 XXX XXX XXX
TRANSFER 1
TRANSFER 2
TRANSFER 3
24 23 16 15 8 7
24 23 16 15 8 7
Figure 7-5. Example of a Misaligned Long-Word Transfer
DATA BUS
31 0
BYTE 1
BYTE 0 BYTE 1
MEMORY
31 0
XXX XXX XXX BYTE 1
BYTE 0 XXX XXX XXX
TRANSFER 1
TRANSFER 2
24 23 16 15 8 7
24 23 16 15 8 7
Figure 7-6. Example of a Misaligned Word Transfer
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