7- 6 M68040 USER’S MANUAL MOTOROLA
Table 7-2. Summary of Access Types versus Bus Signal Encodings
UPA1, UPA0 $0 MMU
$0 $0 $0
SIZ1, SIZ0 L/Line B/W/L/Line Long Word Line B/W/L Byte Byte
TT1, TT0 $0 $0 $0 $1 $2 $3 $3
TM4–TM2 $0 $1,2,5, or 6 $3 or 4 $1 or 5 Function
Int. Level $1–7 $0
TLN1, TLN0 Cache Set
Undefined Undefined Undefined Undefined Undefined
R/ WWrite Read/Write Read/Write Read/Write Read/Write Read Read
Negated Negated Negated Negated
CIOUT Negated MMU
Asserted Negated Negated
1. The UPA1, UPA0, and CIOUT signals are determined by the U1, U0 data and CM bit fields, respectively,
corresponding to the access address.
2. The TLNx signals are defined only for normal push accesses and normal data line read accesses.
3. The LOCK signal is asserted during TAS, CAS, and CAS2 operand accesses and for some table search update
sequences. LOCKE is asserted for the last transfer of each locked sequence of transfers.
4. Refer to Section 5 Signal Description for definitions of the TMx signal encodings for normal, MOVE16,
and alternate accesses.
7.3 MISALIGNED OPERANDS
All M68040 data formats can be located in memory on any byte boundary. A byte operand
is properly aligned at any address; a word operand is misaligned at an odd address; and a
long word is misaligned at an address that is not evenly divisible by 4. However, since
operands can reside at any byte boundary, they can be misaligned. Although the M68040
does not enforce any alignment restrictions for data operands (including PC relative data
addressing), some performance degradation occurs when additional bus cycles are
required for long-word or word operands that are misaligned. For maximum performance,
data items should be aligned on their natural boundaries. All instruction words and
extension words must reside on word boundaries. Attempting to prefetch an instruction
word at an odd address causes an address error exception. Refer to Section 8 Exception
Processing for details on address error exceptions.
The M68040 data memory unit converts misaligned operand accesses that are
noncachable to a sequence of aligned accesses. These aligned accesses are then sent to
the bus controller for completion, always resulting in aligned bus transfers. Misaligned
operand accesses that miss in the data cache are cachable and are not aligned before
line filling. Refer to Section 4 Instruction and Data Caches for details on line fill and the