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7- 4 M68040 USER’S MANUAL MOTOROLA
REGISTER
ADDRESS
$xxxxxxx0
EXTERNAL
DATA BUS
31 024 23 16 15 8 7
BYTE 3 BYTE 2 BYTE 1 BYTE 0
ROUTING
MULTIPLEXER
31 024 23 16 15 8 7
EXTERNAL BUS
INTERNAL TO
THE MC68040
BYTE 3 BYTE 2 BYTE 1 BYTE 0
D31–D24 D23–D16 D15–D8 D7–D0
Figure 7-3. Data Multiplexing
Table 7-1 lists the combinations of the SIZx, A1, and A0 signals, collectively called byte
enable signals, that are used for each of the four sections of the data bus. In the table,
BYTEn indicates the data bus section that is active, the portion of the requested operand
that is read or written during that bus transfer. For line transfers, all bytes are valid as
listed and can correspond to portions of the requested operand or to data required to fill
the remainder of the cache line. The bytes labeled with a dash are not required; they are
ignored on read transfers and driven with undefined data on write transfers. Not selecting
these bytes prevents incorrect accesses in sensitive areas such as I/O devices. Figure 7-4
illustrates a logic diagram for one method for generating byte enable signals from the
SIZx, A1, and A0 and the associated PAL equation. These byte enable signals can be
combined with the address decode logic.
Table 7-1. Data Bus Requirements for Read and Write Cycles
Transfer Signal Encodings Active Data Bus Sections
Size SIZ1 SIZ0 A1 A0 D31–D24 D23–D16 D15–D8 D7–D0
Byte 0
0
0
0
1
1
1
1
0
0
1
1
0
1
0
1
BYTEn
BYTEn
BYTEn
BYTEn
Word 1
1
0
0
0
1
0
0
BYTEn
BYTEn
BYTEn
BYTEn
Long Word 0 0 X X BYTEn BYTE n BYTEn BYTEn
Line 1 1 X X BYTEn BYTEn BYTEn BYTEn
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