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MOTOROLA M68040 USER’S MANUAL 7- 3
7.2 DATA TRANSFER MECHANISM
Figure 7-2 illustrates how the bus designates operands for transfers on a byte boundary
system. The integer unit handles floating-point operands as a sequence of related long-
word operands. These designations are used in the figures and descriptions that follow.
31 0
LONG-WORD OPERAND
WORD OPERAND
BYTE OPERAND
24 23 16 15 8 7
MOST SIGNIFICANT BYTE LEAST SIGNIFICANT BYTE
MOST SIGNIFICANT BYTE LEAST SIGNIFICANT BYTE
BYTE 3 BYTE 2 BYTE 1 BYTE 0
Figure 7-2. Internal Operand Representation
Figure 7-3 illustrates general multiplexing between an internal register and the external
bus. The internal register connects to the external data bus through the internal data bus
and multiplexer. The data multiplexer establishes the necessary connections for different
combinations of address and data sizes.
Unlike the MC68020 and MC68030 processors, the M68040 does not support dynamic
bus sizing and expects the referenced device to accept the requested access width. The
MC68150 dynamic bus sizer is designed to allow the 32-bit M68040, MC68EC040,
MC68LC040 bus to communicate bidirectionally with 32-, 16-, or 8-bit peripherals and
memories. It dynamically recognizes the size of the selected peripheral or memory device
and then reads or writes the appropriate data from that location. Refer to MC68150/D,
MC68150 Dynamic Bus Sizer
, for information on this device.
Blocks of memory that must be contiguous, such as for code storage or program stacks,
must be 32 bits wide. Byte- and word-sized I/O ports that return an interrupt vector during
interrupt acknowledge cycles must be mapped into the low-order 8 or 16 bits, respectively,
of the data bus.
The multiplexer takes the four bytes of the 32-bit bus transfer and routes them to their
required positions. For example, byte 0 would normally be routed to D31–D24, but it can
also be routed to any other byte position supporting a misaligned data transfer. The same
is true for any of the other operand bytes. The transfer size (SIZ0 and SIZ1) and byte
offset (A1 and A0) signals determine the positioning of the bytes (see Table 7-1). The size
indicated on the SIZx signals corresponds to the size of the operand transfer for the entire
bus cycle. During an operand transfer, A31–A2 indicate the long-word base address for
the first byte of the operand to be accessed; A1 and A0 indicate the byte offset from the
base. For a burst-inhibited line transfer, A1 and A0 for each of the four accesses (the
burst-inhibited line transfer and three long-word transfers) are copied from the lowest two
bits of the access address used to initiate the line transfer.
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