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7- 2 M68040 USER’S MANUAL MOTOROLA
negate logic levels. The exceptions to this rule are the TIP, TA , and BB signals that
transition between logic levels during T4 but transition from a driven state to a high-
impedance state during T1. The input setup time (tsu), input hold time (thi ), output hold
time (tho), and delay time (td) illustrated in Figure 7-1 are described in the AC electrical
timing specifications in Section 11 MC68040 Electrical and Thermal Characteristics.
OUTPUTS
INPUTS
BCLK
T1 T2 T3 T4 T1
INTERNALLY
PHASE-LOCKED
PCLK
tho'
td
td'
tho
tsu
thi
= Required input setup time relative to BCLK rising edge.
tsu
= Required input hold time relative to BCLK rising edge.
thi
= Output hold time relative to BCLK rising edge.
tho
tho' = Output hold time relative to BCLK rising edge; = –1/2 PCLK.
tho' th
= Propagation delay of signal relative to BLK rising edge.
td
= Propagation delay of signal relative to PCLK falling edge.
td' ; = –1/2 PCLK
t
d' td
except for TIP, TA, BB when used as outputs.
NOTES:
1.
2.
3.
4.
5.
6.
Figure 7-1. Signal Relationships to Clocks
Inputs to the M68040 (other than the IPL2–IPL0 and RSTI signals) are synchronously
sampled and must be stable during the sample window defined by tsu, thi, and tho (see
Figure 7-1) to guarantee proper operation. The asynchronous IPL≈ and RSTI signals are
also sampled on the rising edge of BCLK, but are internally synchronized to resolve the
input to a valid level before using it. Since the timing specifications for the M68040 are
referenced to the rising edge of BCLK, they are valid only for the specified operating
frequency and must be scaled for lower operating frequencies.
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