restarted, and a proper reentry into any of the four instructions is again required before the
system clocks can be stopped.
Control over the output enable signals using the boundary scan register and the EXTEST
and HIGHZ instructions requires a compatible circuit-board test environment to avoid
destructive configurations. The user is responsible for avoiding situations in which the
M68040 output drivers are enabled into actively driven networks.
The TRST signal provides the ability for an asynchronous reset of the test logic and
requires no internal clocking to force the TAP controller into the test-logic-reset state. This
signal should be asserted during system power-up to initialize the 1149.1A test interface
and avoid the potential for board-level bus conflicts. Essentially the TRST signal provides
the ability to prevent possible board-level bus contention during power-up due to the test
logic having control of the pins. The device has no internal power-up reset circuit. The
TRST signal should be treated similar to the RSTI signal for board design considerations
concerning power-up conditions.
Negation of the TRST signal requires certain precautions to achieve a predictable TAP
controller state. The TMS signal is sampled on the rising edge of TCK and sequences the
TAP controller. If TMS is low and TRST is negated simultaneously with the rising edge of
TCK, the resultant TAP controller state is unpredictable but will be either test-logic-reset or
run-test/idle. To avoid this uncertainty, either 1) the negation of TRST can be synchronized
with the falling edge of TCK or 2) TMS can remain high until after TRST negation.
Alternatively, holding TMS low for two or more TCK periods following TRST negation
ensures that the TAP controller is in the run-test/idle state.
There are two considerations for non-IEEE standard 1149.1A operation. First, TCK does
not include an internal pullup resistor and should not be left unconnected to preclude mid-
level inputs. The second consideration is to ensure that the IEEE standard 1149.1A test
logic remains transparent to the system logic by providing the ability to force the test-logic-
reset state.
Figure 6-7 illustrates disabling the IEEE standard 1149.1A operation through connecting
TRST directly or through a resistor to ground or a suitable logic network. Connecting TRST
to RSTI while TCK is held either high or low meets the two considerations. If a pulse
asserts TRST , the TAP controller is forced into the test-logic-reset state and can remain in
this state as long as a rising edge on the TCK signal does not occur when TMS is low.
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