Table 6-2. Boundary Scan Bit Definitions (Concluded)
Bit Cell Type
Name Pin Type
Ctrl Cell
148 I.Pin SIZ1 I/O io.0
149 O.Latch LOCK TS-Output2io.1
150 IO.Ctl io.ab (Note 4)
151 IO.Ctl io.db (Note 4)
152 O.Latch MI Output2(Note 3)
153 O.Latch BR Output2(Note 3)
154 IO.Ctl io.2 (Note 4)
155 IO.Ctl io.1 (Note 4)
156 IO.Ctl io.0 (Note 4)
157 O.Latch TS I/O2io.0
158 I.Pin TS I/O io.0
159 O.Latch BB I/O2io.1
160 I.Pin BB I/O io.1
161 O.Latch TIP TS-Output2io.1
162 O.Latch PST3 Output2(Note 3)
163 O.Latch PST2 Output2(Note 3)
164 O.Latch PST1 Output2(Note 3)
165 O.Latch PST0 Output2(Note 3)
Bit Cell Type
Name Pin Type
Ctrl Cell
166 O.Latch TA I/O2io.2
167 I.Pin TA I/O io.2
168 I.Pin TEA Input —
169 I.Pin BG Input —
170 I.Pin SC1 Input
171 I.Pin SC0 Input
172 I.Pin TBI Input —
173 I.Pin AVEC Input —
174 I.Pin TCI Input —
175 I.Pin DLE5Input —
176 I.Pin PCLK Input —
177 I.Pin BCLK Input —
178 I.Pin IPL0 Input —
179 I.Pin IPL1 Input —
180 I.Pin IPL2 Input —
181 I.Pin RSTI Input —
182 I.Pin CDIS Input —
183 I.Pin MDIS6Input —
1. I.Pin, IO.Ctl, and O.Latch are equivalent to the BSDL descriptions: BC_4, BC_2, and BC_2, respectively.
2. Boundary scan register bit positions that are used during the drive control (DRVCTL.X) instructions.
3. These output-only cells can be turned off (high impedance) by using the HIGHZ instruction.
4. All of the control signals (IO.Ctl) are cleared in the test-logic-reset state.
5. Renamed JS0 on the MC68LC040 and MC68EC040.
6. Renamed JS1 on the MC68EC040.
The test logic is implemented using static logic design, and TCK can be stopped in either
a high or low state without loss of data. The system logic, however, includes considerable
dynamic logic. For this reason, the system clocks (PCLK and BCLK) cannot be stopped or
allowed to run slower than the specified frequency except when the EXTEST, HIGHZ,
DRVCTL.T, or SHUTDOWN instructions have been properly invoked.
PCLK and BCLK must be kept running for two additional BCLK periods upon initial entry
into any of the four instructions, EXTEST, HIGHZ, DRVCTL.T, or SHUTDOWN. This
restriction is necessary to allow time for an internal reset to propagate through an internal
synchronizer. After this period, the user has complete time-domain freedom with the two
system clock pins. After any of the four instructions has been properly entered, these
instructions can be executed in any order without a time-domain clocking restriction.
Entering any instruction other than one of these four requires that the system clocks be
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