6- 6 M68040 USER’S MANUAL MOTOROLA
has control of the I/O pins. The 1149.1A interface is transparent to system operation
except for drive control selection during execution of this instruction.
When the system logic has control of the signal I/O directions and levels, the drive control
latches are loaded from the IPL2–IPL0 pins at the negation of the RSTI signal. After RSTI
has been negated, and the 128-clock internal reset cycle has expired (see Section 7 Bus
Operation), the DRVCTL.S instruction is executed. Each drive control latch is modified
during the update-DR state. Any subsequent RSTI signal negation while in a system
configuration (i.e., system logic has control of the signal I/O directions and levels) can
cause the drive control latches to be overwritten with new IPL¯ signal values. The system
bus can be suspended in a wait state while this function is being performed.
The BYPASS instruction selects the single-bit bypass register, creating a single-bit shift-
register path from TDI to the bypass register to TDO. The instruction enhances test
efficiency when a component other than the M68040 becomes the device under test.
When the bypass register is initially selected, the instruction shift register stage is set to a
logic zero on the rising edge of TCK following entry into the capture-DR state. Therefore,
the first bit to be shifted out after selecting the bypass register is always a logic zero.
Figure 6-2 illustrates the bypass register.
Figure 6-2. Bypass Register
6.3 BOUNDARY SCAN REGISTER
The 184-bit boundary scan register uses the TAP controller to scan user-defined values
into the output buffers, capture values presented to input pins, and control the direction of
bidirectional pins. The instruction shift register cell nearest TDO (i.e., first to be shifted out)
is defined as bit zero. The last bit to be shifted out is bit 183. This register includes cells
for all device signal pins and clock pins along with associated control signals.
The M68040 boundary scan register consists of three cell structure types, O.Latch, I.Pin,
and IO.Ctl, that are associated with a boundary scan register bit. All boundary scan output
cells capture the logic level of the device output latch during the capture-DR state. Figures
6-3 through 6-5 illustrate these three cell types. Figure 6-6 illustrates the general
arrangement of these cells.