MOTOROLA M68040 USER’S MANUAL 6- 5
The DRVCTL.T instruction is intended to be used in test applications in conjunction with
the EXTEST and SHUTDOWN instructions and not for system applications. It therefore
differs from DRVCTL.S in that this instruction invokes the keep-alive clock, asserts the
internal reset, and the test logic, not the system logic, has control of the I/O pins.
When the system logic has control of signal pin I/O directions and levels, the drive control
latch is loaded from the IPL2–IPL0 pins during the negation of RSTI. DRVCTL.T overwrites
this value with boundary scan data in the update-DR state. The selected output driver
state remains unchanged if only the DRVCTL.T, EXTEST, or SHUTDOWN instructions
are invoked. If an instruction other than one of these three is executed, the system logic
protocol regains control of the output driver state and overwrites the value that the
DRVCTL.T instruction previously defined.
Note that the output drive control state does not change while the 1149.1A instruction is
one of the three instructions DRVCTL.T, EXTEST, or SHUTDOWN. If DRVCTL.T changes
the output driver state and then the test-logic-reset state is entered, the instruction shift
register is reset to BYPASS, and the system logic can change the output driver state.
This instruction provides an opcode for automatic test pattern generation (ATPG)
programs to cope with the clocking protocol required to stop the system clocks. This
instruction asserts internal system reset, activates an internal keep alive clock, and selects
the bypass register. Internal decoding of the instruction selects the bypass register, and
the test logic, not the system logic, has control of the I/O ports. Note that initializing the
boundary scan data register and then selecting the SHUTDOWN instruction provides a
clamping function. The test logic controls the I/O state, and the bypass register is
Motorola reserves this instruction for manufacturing use. The instruction does not change
pin I/O as defined for system operation.
The DRVCTL.S instruction controls the output driver selection on a pin-by-pin basis. This
instruction allows data in the boundary scan register to select the output driver during the
update-DR state when the system logic has control of the signal I/O directions and levels.
A logic zero selects the large buffer or driver; a logic one selects the small buffer or driver
(see Table 6-1).
The DRVCTL.S instruction is intended to be used in system applications and not in test
applications. In system applications, the system logic has control of the signal pin I/O
directions and levels; whereas, in test applications, the 1149.1A test logic has control of it.
It therefore differs from DRVCTL.T in that this instruction does not invoke the internal keep
alive clock, it does not assert the internal reset, and the system logic, not the test logic,