EXTEST asserts internal reset for the M68040 system logic to force a predictable benign
internal state and activates an internal keep-alive clock to protect the device from potential
internal damage. This internal clock eliminates the requirement to keep the system clocks
(PCLK and BCLK) running during EXTEST operations and allows these two system clock
pins to be included in boundary scan testing.
6.2.2 HIGHZ
The HIGHZ instruction is an optional instruction provided as a Motorola public instruction
to anticipate the need to backdrive output pins during circuit board testing. The HIGHZ
instruction activates an internal keep-alive clock, asserts internal system reset, selects the
bypass register, and forces all output and bidirectional pins to the high-impedance state.
Asserting TRST or holding TMS high and clocking TCK for at least five rising edges
causes the TAP controller to enter the test-logic-reset state. Using only the TMS and TCK
pins and the capture-IR and update-IR states invokes the HIGHZ instruction. This scheme
works because the value captured by the instruction shift register during the capture-IR
state is identical to the HIGHZ opcode.
The SAMPLE/PRELOAD instruction provides two separate functions. First, it provides a
means to obtain a sample system data and control signal. Sampling occurs on the rising
edge of TCK in the capture-DR state. The user can observe the data by shifting it through
the boundary scan register to output TDO using the shift-DR state. Both the data capture
and the shift operations are transparent to system operation. The user must provide some
form of external synchronization to achieve meaningful results since there is no internal
synchronization between TCK and BCLK.
The second function of the SAMPLE/PRELOAD instruction is to initialize the boundary
scan register output cells before selecting EXTEST, which is accomplished by ignoring
data being shifted out of TDO while shifting in initialization data. The update-DR state can
then be used to initialize the boundary scan register and ensure that known data and
output state will occur on the outputs after entering the EXTEST instruction.
6.2.4 DRVCTL.T
The DRVCTL.T instruction is a Motorola public instruction that provides the ability to select
one of two output drivers on a pin-by-pin basis. It is intended for use with EXTEST or
SHUTDOWN to provide an IEEE-compatible environment to select the output drivers for
board-level test environments. This instruction allows data in the boundary scan register to
select the output driver. A logic zero in the appropriate boundary scan output cell (see
Table 6-1) selects the large buffer, and a logic one selects the small buffer (see Section 7
Bus Operation). Data captured in the capture-DR state for this instruction is identical to
that captured during EXTEST: output data cells for outputs and pin state for inputs. Note
that no data relevant to the drive control function is captured during the capture-DR state.
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