6- 2 M68040 USER’S MANUAL MOTOROLA
Figure 6-1 illustrates a block diagram of the M68040 implementation of IEEE standard
1149.1A. The test logic includes a 16-state dedicated TAP controller. These 16 controller
states are defined in detail in the IEEE standard 1149.1A, but only 8 are included in this
The TAP controller provides access to five dedicated signal pins:
TCK—A test clock input that synchronizes the test logic.
TMS—A test mode select input with an internal pullup resistor sampled on the rising
edge of TCK to sequence the TAP controller.
TDI—A test data input with an internal pullup resistor sampled on the rising edge of
TDO—A three-state test data output actively driven only in the shift-IR and shift-DR
controller states that changes on the falling edge of TCK.
TRST —An active-low asynchronous reset with an internal pullup resistor that forces
the TAP controller into the test-logic-reset state.
The test logic also includes an instruction shift register and two test data registers, a
boundary scan register and a bypass register. The boundary scan register links all device
signal pins into the instruction shift register.
3-BIT INSTRUCTION SHIFT REGISTER
184-BIT BOUNDARY SCAN REGISTER
TEST DATA REGISTERS
Figure 6-1. M68040 Test Logic Block Diagram