MOTOROLA M68040 USER’S MANUAL 6- 1
IEEE 1149.1A TEST ACCESS PORT (JTAG)
This section does not apply to the MC68040V and
MC68EC040V. Refer to Appendix C MC68040V and
MC68EC040 for details. All references to M68040 in this
section only, refer to the MC68040, MC68LC040, and
The M68040 includes dedicated user-accessible test logic that is fully compatible with the
IEEE standard 1149.1A
Standard Test Access Port and Boundary Scan Architecture
Problems associated with testing high-density circuit boards have led to the standard’s
development under the sponsorship of the IEEE Test Technology Committee and the
Joint Test Action Group (JTAG).
This section is to be used in conjunction with the supporting IEEE document and includes
those chip-specific items that the IEEE standard requires to be defined and additional
information specific to the M68040 implementation. For example, the IEEE standard
1149.1A test access port (TAP) controller states are referenced in this section but are not
described. For these details and application information regarding the standard, refer to
the IEEE standard 1149.1A document.
The M68040 implementation supports circuit board test strategies based on the standard.
The test logic utilizes static logic design and is system logic independent of the device.
The M68040 implementation provides capabilities to:
a. Perform boundary scan operations to test circuit board electrical continuity,
b. Bypass the M68040 by reducing the shift register path to a single cell,
c. Sample the M68040 system pins during operation and transparently shift out the
d. Disable the output drive to output-only pins during circuit board testing, and
e. Select one of two output drivers on a pin-by-pin basis.
The IEEE standard 1149.1A test logic cannot be considered
completely benign to those planning not to use this capability.
Certain precautions must be observed to ensure that this logic
does not interfere with system operation. Refer to 6.5
Disabling the IEEE Standard 1149.1A Operation.