Table 5-7 provides a summary of the electrical characteristics of the signals discussed in
this section.
Table 5-7. Signal Summary
Signal Name Mnemonic Type Active Three-State
Address Bus A31–A0 Input/Output High Yes
Autovector AVEC Input Low
Bus Busy BB Input/Output Low Yes
Bus Clock BCLK Input —
Bus Grant BG Input Low
Bus Request BR Output Low No
Cache Disable CDIS Input Low
Cache Inhibit Out CIOUT Output Low Yes
Data Bus D31–D0 Input/Output High Yes
Data Latch Enable1DLE Input High —
Ground GND Ground
Interrupt Pending IPEND Output Low No
Interrupt Priority Level2IPL2IPL0 Input Low
Bus Lock LOCK Output Low Yes
Bus Lock End LOCKE Output Low Yes
Memory Inhibit MI Output Low No
MMU Disable3MDIS Input Low
Processor Clock PCLK Input —
Processor Status PST3–PST0 Output High No
Read/Write R/WInput/Output High/Low Yes
Reset In RSTI Input Low
Reset Out RSTO Output Low No
Snoop Control SC1, SC0 Input High —
Transfer Acknowledge TA Input/Output Low Yes
Transfer Burst Inhibit TBI Input Low
Transfer Cache Inhibit TCI Input Low
Transfer Error Acknowledge TEA Input Low
Transfer in Progress TIP Output Low Yes
Transfer Line Number TLN1, TLN0 Output High Yes
Transfer Modifier TM2–TM0 Output High Yes
Transfer Size SIZ1, SIZ0 Input/Output High Yes
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