MOTOROLA M68040 USER’S MANUAL 5- 15
5.12 TEST SIGNALS
The M68040 includes dedicated user-accessible test logic that is fully compatible with the
Standard Test Access Port and Boundary Scan Architecture
associated with testing high-density circuit boards have led to the development of this
standard under the IEEE Test Technology Committee and Joint Test Action Group (JTAG)
sponsorship. The M68040 implementation supports circuit board test strategies based on
this standard. However, the JTAG interface is not intended to provide an in-circuit test to
verify M68040 operations; therefore, it is impossible to test M68040 operations using this
interface. Section 6 IEEE 1149.1 Test Access Port (JTAG) describes the M68040
implementation of the IEEE 1149.1 and is intended to be used with the supporting IEEE
5.12.1 Test Clock (TCK)
This input signal is used as a dedicated clock for the test logic. Since clocking of the test
logic is independent of the normal operation of the MC68040, several other components
on a board can share a common test clock with the processor even though each
component may operate from a different system clock. The design of the test logic allows
the test clock to run at low frequencies, or to be gated off entirely as required for test
5.12.2 Test Mode Select (TMS)
This input signal is decoded by the TAP controller and distinguishes the principle
operationas of the test support circuitry.
5.12.3 Test Data In (TDI)
This input signal provides a serial data input to the TAP.
5.12.4 Test Data Out (TDO)
This three-state output signal provides a serial data output from the TAP. The TDO output
can be placed in a high-impedance mode to allow parallel connection of board-level test
5.12.5 Test Reset ( )—Not on MC68040V and MC68EC040V
This input signal provides an asynchronous reset of the TAP controller.
5.13 POWER SUPPLY CONNECTIONS
The M68040 requires connection to a VCC power supply, positive with respect to ground.
The VCC and ground connections are grouped to supply adequate current to the various
sections of the processor. Section 12 Ordering Information and Mechanical Data
describes the groupings of VCC and ground connections.