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5- 12 M68040 USER’S MANUAL MOTOROLA
5.8.2 Interrupt Pending Status ( )
This output signal indicates that an interrupt request has been recognized internally and
exceeds the current interrupt priority mask in the status register (SR). External devices
(other bus masters) can use IPEND to predict processor operation on the next instruction
boundaries. IPEND is not intended for use as an interrupt acknowledge to external
peripheral devices. Refer to Section 7 Bus Operation for bus information related to
interrupts and to Section 8 Exception Processing for interrupt information.
5.8.3 Autovector ( )
This input signal is asserted with TA during an interrupt acknowledge transfer to request
internal generation of the vector number. Refer to Section 7 Bus Operation for more
information about automatic vectors.
5.9 STATUS AND CLOCK SIGNALS
The following paragraphs explain the signals that provide timing, test control, and the
internal processor status.
5.9.1 Processor Status (PST3–PST0)
These outputs indicate the internal execution unit’s status. The timing is synchronous with
BCLK, and the status may have nothing to do with the current bus transfer. The PSTx
signal is updated depending on the type of PSTx encoding. There are two classes of
PSTx encodings. The first class is associated with instruction boundaries, and the second
class indicates the processor’s present status. Table 5-6 lists the definition of the
encodings.
The encodings 0, 8, 4, 5, C, D, E, and F indicate the present status and do not reflect a
specific stage of the pipe. These encodings persist as long as the processor stays in the
indicated state. The default encoding 0 (user) or 8 (supervisor) is indicated if none of the
above conditions apply. The encodings 1, 2, 3, 9, A, and B belong to the first class of
PSTx encoding. This class indicates that the instruction is in its last instruction execution
stage. These encodings exist for only one BCLK period per instruction and are mutually
exclusive.
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