the access. During alternate bus master accesses, the M68040 samples TEA to detect
completion of each bus transfer.
5.4.5 Transfer Cache Inhibit ( )
This input signal inhibits read data from being loaded into the M68040 instruction or data
caches. TCI is ignored during all writes and after the first data transfer for both burst line
reads and burst-inhibited line reads. TCI is also ignored during all alternate bus master
5.4.6 Transfer Burst Inhibit ( )
This input signal indicates to the processor that the accessed device cannot support burst
mode accesses and that the requested line transfer should be divided into individual long-
word transfers. Asserting TBI with TA terminates the first data transfer of a line access,
which causes the processor to terminate the burst and access the remaining data for the
line as three successive long-word transfers. During alternate bus master accesses, the
M68040 samples the TBI to detect completion of each bus transfer.
The following signals control the operation of the M68040 on-chip snoop logic. Section 4
Instruction and Data Caches provides information about the relationship of the snoop
control signals to the caches, and Section 7 Bus Operation discusses the relationship of
these signals to bus operation.
5.5.1 Snoop Control (SC1, SC0)
These input signals specify the snoop operation to be performed by the M68040 for an
alternate bus master transfer. If the M68040 is allowed to snoop an alternate bus master
read transfer, it can intervene in the access to supply data from its data cache when the
memory copy is stale, ensuring that the alternate bus master receives valid data. Writes
by an alternate bus master can also be snooped to either update the M68040 internal data
cache with the new data or invalidate the matching cache lines, ensuring that subsequent
M68040 reads access valid data. These signals are ignored when the processor is the bus
5.5.2 Memory Inhibit ( )
This output signal prevents an alternate bus master from accessing possibly stale data in
memory while the M68040 is unable to respond. MI is asserted during reset preventing
external memory from responding. When the SCx signals indicate an access should be
snooped, the M68040 keeps MI asserted until it determines if intervention in the access is
required. If no intervention is required, MI is negated and memory is allowed to respond to
complete the access. Otherwise, MI remains asserted and the M68040 completes the
transfer as a slave. It updates its caches on a write or supplies data to the alternate bus
master on a read. MI is negated when the M68040 is the bus master. During a snoop
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