three-stating. Do not use LOCKE if it is possible to retry the last write of a read-write-
modify operation.
5.3.9 Cache Inhibit Out ( )
This three-state output reflects the state of the cache mode field in one of the address
translation caches and is asserted for accesses to noncachable pages to indicate that an
external cache should ignore the bus transfer. When the referenced logical address is
within an area specified for transparent translation, the cache mode field of the
appropriate transparent translation register controls the state of CIOUT. Refer to Section
3 Memory Management Unit (Except MC68EC040 and MC68EC040V) for more
information about the address translation caches and transparent translation. When the
M68040 is not the bus master, the CIOUT signal is set to a high-impedance state.
The following signals provide control functions for bus transfers. Refer to Section 7 Bus
Operation for detailed information about the relationship of the bus transfer control
signals to bus operation.
5.4.1 Transfer Start ( )
The processor asserts this three-state bidirectional signal for one clock period to indicate
the start of each transfer. During alternate bus master accesses, the processor monitors
this signal to detect the start of each transfer to be snooped.
5.4.2 Transfer in Progress ( )
This three-state output is asserted to indicate that a bus transfer is in progress and is
negated during idle bus cycles if the bus is still granted to the processor. When the
processor loses the bus, TIP negates after completion of the current transfer and goes to
a high-impedance state. Note that TIP is kept asserted on back-to-back bus cycles.
5.4.3 Transfer Acknowledge ( )
This three-state bidirectional signal indicates the completion of a requested data transfer
operation. During transfers by the M68040, TA is an input signal from the referenced slave
device indicating completion of the transfer. During alternate bus master accesses, TA is
normally three-stated to allow the referenced slave device to respond, and the M68040
samples it to detect the completion of each bus transfer. The M68040 can inhibit memory
and intervene in the access to source or sink data in its internal caches by asserting TA to
acknowledge the data transfer. This capability applies to alternate bus master accesses
that reference modified (dirty) data in the M68040 caches.
5.4.4 Transfer Error Acknowledge ( )
The current slave asserts this input signal to indicate an error condition for the bus
transaction. When asserted with TA, this signal indicates that the processor should retry
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