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5- 4 M68040 USER’S MANUAL MOTOROLA
MC68040
VCC
GND
BUS ARBITRATION
BG
BR
BB
BUS SNOOP CONTROL 
AND RESPONSE
M I
INTERRUPT 
CONTROL
IPL03
AVEC
IPEND
PROCESSOR 
CONTROL
CDIS
RSTI
RSTO
PCLK4
BCLK
TEST
TRST4
TMS
TCK
TDI
POWER SUPPLY
TDO
SC0
SC1
IPL13
IPL23
STATUS AND 
CLOCKS
PST0
PST1
PST2
DATA BUS D31–D0
TRANSFER
ATTRIBUTES
MASTER
TRANSFER
CONTROL
A31–A0
ADDRESS
BUS
TS
TIP
TCI
SLAVE
TRANSFER
CONTROL
TEA
TBI
R/W
LOCKE
CIOUT
TT0
TT1
TM0
TM1
TM2
TLN0
TLN1
UPA0
UPA1
SIZ0
SIZ1
LOCK
TA
DLE1
MDIS2
1. This signal is only available on the MC68040.
2. This signal is not available on the MC68EC040 and MC68EC040V.
3. These signals are different on power-up for the MC68LC040 and MC68EC040.
4. These signals are not available on the MC68040V and MC68EC040V.
NOTES:
PST3
Figure 5-1. Functional Signal Groups
5.1 ADDRESS BUS (A31–A0)
These three-state bidirectional signals provide the address of the first item of a bus
transfer (except for acknowledge transfers) when the M68040 is the bus master. When an
alternate bus master is controlling the bus, the processor examines (snoops) these signals
to determine whether the processor should intervene in the access to maintain cache
coherency.
The level on CDIS can select a multiplexed bus mode during processor reset, which
allows the address bus and data bus to be physically tied together for multiplexed bus
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