Table 5-1. Signal Index
Signal Name Mnemonic Function
Address Bus A31–A0 32-bit address bus used to address any of 4-Gbytes.
Data Bus D31–D0 32-bit data bus used to transfer up to 32 bits of data per bus transfer.
Transfer Type TT1,TT0 Indicates the general transfer type: normal, MOVE16, alternate logical
function code, and acknowledge.
Transfer Modifier TM2–TM0 Indicates supplemental information about the access.
Transfer Line Number TLN1,TLN0 Indicates which cache line in a set is being pushed or loaded by the current
line transfer.
UPA1,UPA0 User-defined signals, controlled by the corresponding user attribute bits from
the address translation entry.
Read/Write R/WIdentifies the transfer as a read or write.
Transfer Size SIZ1,SIZ0 Indicates the data transfer size. These signals, together with A0 and A1,
define the active sections of the data bus.
Bus Lock LOCK Indicates a bus transfer is part of a read-modify-write operation, and the
sequence of transfers should not be interrupted.
Bus Lock End LOCKE Indicates the current transfer is the last in a locked sequence of transfers.
Cache Inhibit Out CIOUT Indicates the processor will not cache the current bus transfer.
Transfer Start TS Indicates the beginning of a bus transfer.
Transfer in Progress TIP Asserted for the duration of a bus transfer.
Transfer Acknowledge TA Asserted to acknowledge a bus transfer.
Transfer Error
TEA Indicates an error condition exists for a bus transfer.
Transfer Cache Inhibit TCI Indicates the current bus transfer should not be cached.
Transfer Burst Inhibit TBI Indicates the slave cannot handle a line burst access.
Data Latch Enable1DLE Alternate clock input used to latch input data when the processor is operating
in DLE mode.
Snoop Control SC1,SC0 Indicates the snooping operation required during an alternate master access.
Memory Inhibit MI Inhibits memory devices from responding to an alternate master access
during snooping operations.
Bus Request BR Asserted by the processor to request bus mastership.
Bus Grant BG Asserted by an arbiter to grant bus mastership to the processor.
Bus Busy BB Asserted by the current bus master to indicate it has assumed ownership of
the bus.
Cache Disable CDIS Dynamically disables the internal caches to assist emulator support.
MMU Disable2MDIS Disables the translation mechanism of the MMUs.
Reset In RSTI Processor reset.
Reset Out RSTO Asserted during execution of a RESET instruction to reset external devices.
Interrupt Priority Level3IPL2—IPL0 Provides an encoded interrupt level to the processor.
Interrupt Pending IPEND Indicates an interrupt is pending.
Autovector AVEC Used during an interrupt acknowledge transfer to request internal generation
of the vector number.
Processor Status PST3–PST0 Indicates internal processor status.
Bus Clock BCLK Clock input used to derive all bus signal timing.
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