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MOTOROLA M68040 USER’S MANUAL 4- 17
Table 4-4. Data-Cache Line State Transitions
Current State
Cache Operation Invalid Cases Valid Cases Dirty Cases
CPU Read Miss I1 Read line from
memory; supply data
to CPU and update
cache; go to valid
state.
V1 Read line from
memory; supply data
to CPU and update
cache (replacing old
line); remain in current
state.
D1 Buffer dirty cache line;
read new line from
memory; supply data
to CPU and update
cache; write buffered
dirty data to memory;
go to valid state.
CPU Read Hit I2 Not Possible V2 Supply data to CPU;
remain in current state.
D2 Supply data to CPU;
remain in current state.
CPU Write Miss
(Copyback)
I3 Read line from
memory into cache;
write data to cache;
set Dn bits of modified
long words; go to dirty
state.
V3 Read line from
memory into cache
(replacing old line);
write data to cache
and set Dn bits; go to
dirty state.
D3 Buffer dirty cache line;
read new line from
memory; write data to
cache and set Dn bits;
write buffered dirty
data to memory;
remain in current state.
CPU Write Miss
(Write-through)
I4 Write data to memory;
remain in current state.
V4 Write data to memory;
remain in current state.
D4 Write data to memory;
remain in current state
(see note).
CPU Write Hit
(Copyback)
I5 Not Possible V5 Write data into cache;
set Dn bits of modified
long words; go to dirty
state.
D5 Write data in cache;
set Dn bits of modified
long words; remain in
current state.
CPU Write Hit
(Write-through)
I6 Not Possible V6 Write data to cache;
write data to memory;
remain in current state.
D6 Write data into cache
(no change to Dn bits);
write data to memory;
remain in current state
(see note).
Cache Invalidate
(CINV)
I7 No action; remain in
current state.
V7 No action; go to invalid
state.
D7 No action (dirty data
lost); go to invalid
state.
Cache Push
(CPUSH)
I8 No action; remain in
current state.
V8 No action; go to invalid
state.
D8 Write dirty data to
memory; go to invalid
state.
Alternate Master Read Hit
(Snoop Control = 01
— Leave Dirty)
I9 Not Possible V9 No action; remain in
current state.
D9 Inhibit memory and
source data; remain in
current state.
NOTE: Dirty state transitions D4 and D6 are the result of a system programming error and should be avoided even
though they are technically valid.
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