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MOTOROLA M68040 USER’S MANUAL 4- 15
Table 4-3. Instruction-Cache Line State Transitions
Current State
Cache Operation Invalid Cases Valid Cases
CPU Read Miss I1 Read line from memory;
supply data to CPU and
update cache; go to valid
state.
V1 Read line from memory; supply
data to CPU and update cache
(replacing old line); remain in
current state.
CPU Read Hit I2 Not Possible V2 Supply data to CPU; remain in
current state.
Cache Invalidate or Push
(CINV or CPUSH)
I3 No action; remain in
current state.
V3 No action; go to invalid state.
Alternate Master Read Hit
(Snoop Control = 01 — Leave Dirty)
I4 Not possible; not snooped. V4 Not possible; not snooped.
Alternate Master Read Hit
(Snoop Control = 10 — Invalidate)
I5 Not Possible V5 No action; go to invalid state.
Alternate Master Write Hit
(Snoop Control = 01 — Leave Dirty or
Snoop Control = 10 — Invalidate)
I6 Not Possible V6 No action; go to invalid state.
4.7.2 Data Cache
The IU uses the data cache to store operand data as it generates the data. The data
cache supports a line-based protocol allowing individual cache lines to be in one of three
states: invalid, valid, or dirty. To maintain coherency with memory, the data cache
supports both write-through and copyback modes, specified by the CM field for the page.
Read misses and write misses to copyback pages cause the cache controller to read a
new cache line from memory into the cache. If available, an invalid line in the selected set
is updated with the tag and data from memory. The line state then changes from invalid to
valid by setting the V-bit for the line. If all lines in the set are already valid or dirty, the
pseudo-random replacement algorithm is used to select one of the four lines and replace
the tag and data contents of the line with the new line information. Before replacement,
dirty lines are temporarily buffered and later copied back to memory after the new line has
been read from memory. If a snoop access occurs before the buffered line is written to
memory, the snoop controller snoops the buffer and the caches. Figure 4-6 illustrates the
three possible states for a data cache line, with the possible transitions caused by either
the processor or snooped accesses. Transitions are labeled with a capital letter, indicating
the previous state, followed by a number indicating the specific case listed in Table 4-4.
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