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MOTOROLA M68040 USER’S MANUAL 4- 13
read resulting from a write miss in copyback mode is cache inhibited, the write access
misses in the cache and writes through to memory.
4.6.2 Cache Pushes
When the cache controller selects a dirty data cache line for replacement, memory must
be updated with the dirty data before the line is replaced. This occurs when a CPUSH
instruction execution explicitly selects the cache and when a cache inhibit access hits in
the cache. To reduce the requested data’s latency in the new line, the dirty line being
replaced is temporarily placed in a push buffer while the new line is fetched from memory.
When a line is allocated to the push buffer, an alternate bus master can snoop it, but the
execution units cannot access it. After the bus transfer for the new line successfully
completes, the dirty cache line is copied back to memory, and the push buffer is
invalidated. If the operation to access the replacement line is abnormally terminated or
signaled as cache inhibited, the line in the push buffer is copied back into its original
position in the cache, and the processor continues operation as described in the previous
paragraphs.
The number of dirty long words in the line to be pushed determines the size of the push
transfer on the bus, minimizing bus bandwidth required for the push. A single long word is
written to memory using a long-word push transfer if it is dirty. A push transfer is
distinguished from a normal write transfer by an encoding of 000 on the transfer modifier
signals (TM2–TM0) for the push. Asserting TA and TEA retries the transfer; a bus-error -
asserted TEA terminates it. If a bus error terminates a push transfer, the processor
immediately takes an exception.
A line containing two or more dirty long words is copied back to memory, using a line push
transfer. For a line push, the bus controller requests a burst write transfer by indicating a
line access with SIZ1 and SIZ0. The responding device sequentially accepts four long
words of data. If the responding device does not support the burst mode, it should assert
TBI for the first long word of the line access. The bus controller responds by terminating
the line access and completes the remainder of the line push as three, sequential, long-
word writes. The first cycle of the burst can be retried, but the bus controller interprets a
retry for any of the three remaining cycles as a bus error. If a bus error occurs in any cycle
in the line push transfer, the processor immediately takes an exception.
A dirty cache line hit by a cache-inhibited access is pushed before the external bus access
occurs. If the access is part of a locked transfer sequence for TAS, CAS, or CAS2
operand accesses or translation table updates, the LOCK signal is also asserted for the
push access.
4.7 CACHE OPERATION SUMMARY
The instruction and data caches function independently when servicing access requests
from the IU. The following paragraphs discuss the operational details for the caches and
present state diagrams depicting the cache line state transitions.
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